However, SIMD only temporarily closes the gap, SSE, SSE2 and SSE3 are additional steps that all fall under the same umbrella of providing a temporary remedy for an increasingly worse ratio between the CPU’s execution units and its I/O interface. A larger cache is another solution, in that more data can be held in a superfast on-chip memory that operates at clock speed, that is, independent of the multiplier. In the case of the Prescott, the larger cache is bought at the expense of its access speed as we showed in our original Prescott coverage. Increased latencies are found on the Level2 as well as on the L1 data and trace execution caches and those latencies are amongst the features that partially negate the increase in size.
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